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Subject[PATCH RFC 5/5] ARM: dts: qcom: msm8974-hammerhead: add USB OTG support
Date
From: Jonathan Marek <jonathan@marek.ca>

Add the device tree bindings for USB OTG support. Driver was tested
using on a LG Nexus 5 (hammerhead) phone.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Signed-off-by: Brian Masney <masneyb@onstation.org>
Tested-by: Brian Masney <masneyb@onstation.org>
---
See my cover letter for a question about how I can convert this patch
over to use a gpio-hog to get rid of the otg-en-gpios property.

.../qcom-msm8974-lge-nexus5-hammerhead.dts | 54 +++++++++++++++++++
arch/arm/boot/dts/qcom-msm8974.dtsi | 11 ++++
2 files changed, 65 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts
index e67d61f25a96..71e308d8628d 100644
--- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts
+++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts
@@ -243,6 +243,16 @@
};
};

+ i2c1_pins: i2c1 {
+ mux {
+ pins = "gpio2", "gpio3";
+ function = "blsp_i2c1";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
i2c3_pins: i2c3 {
mux {
pins = "gpio10", "gpio11";
@@ -382,6 +392,25 @@
};
};

+ i2c@f9923000 {
+ status = "ok";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ clock-frequency = <100000>;
+ qcom,src-freq = <50000000>;
+
+ charger: bq24192@6b {
+ compatible = "ti,bq24192";
+ reg = <0x6b>;
+ interrupts-extended = <&spmi_bus 0 0xd5 0 IRQ_TYPE_EDGE_FALLING>;
+
+ omit-battery-class;
+
+ otg-en-gpios = <&pm8941_gpios 35 GPIO_ACTIVE_HIGH>;
+ usb_otg_vbus: usb-otg-vbus { };
+ };
+ };
+
i2c@f9925000 {
status = "ok";
pinctrl-names = "default";
@@ -399,6 +428,31 @@
amstaos,proximity-diodes = <0>;
};
};
+
+ usb@f9a55000 {
+ status = "ok";
+
+ phys = <&usb_hs1_phy>;
+ phy-select = <&tcsr 0xb000 0>;
+
+ extcon = <&charger>, <&usb_id>;
+ vbus-supply = <&usb_otg_vbus>;
+
+ hnp-disable;
+ srp-disable;
+ adp-disable;
+
+ ulpi {
+ phy@a {
+ status = "ok";
+
+ v1p8-supply = <&pm8941_l6>;
+ v3p3-supply = <&pm8941_l24>;
+
+ qcom,init-seq = /bits/ 8 <0x1 0x64>;
+ };
+ };
+ };
};

&spmi_bus {
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index a808973f9dc7..0bd584695ae8 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -704,6 +704,17 @@
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
};

+ i2c@f9923000 {
+ status = "disabled";
+ compatible = "qcom,i2c-qup-v2.1.1";
+ reg = <0xf9923000 0x1000>;
+ interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
i2c@f9924000 {
status = "disabled";
compatible = "qcom,i2c-qup-v2.1.1";
--
2.17.1
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