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SubjectRe: [RFC,05/10] x86/speculation: Add basic IBRS support infrastructure
On Mon, Jan 29, 2018 at 02:25:12PM -0800, Andi Kleen wrote:
> I agree with your point that the common hypervisor practice to fake
> old model numbers will break some of the workarounds. Hypervisors
> may need to revisit their practice.
> > > In general, making these kinds of decisions based on F/M/S is probably
> > > unwise when running in a VM.
> >
> > Certainly. That's why I suggest not trusting f/m/s unless the
> > hypervisor is explicitly saying it's accurate.
> This would be only useful if there's an useful result of this
> non trust.
> But there isn't. Except for panic there's nothing you could do.
> And I don't think panic would be reasonable.

Why it isn't an useful result to enable the Skylake workaround if
unsure about the host CPU?

> The "Skylake bit " or "not skylake bit" doesn't make any sense
> to me. If a hypervisor wants to enable Skylake workarounds
> they need to provide the Skylake model number. If they don't
> think they need them because the VM can never be migrated
> to Skylake, then they don't need to set that model
> number.
> So there isn't any need for inventing any new bits, it's
> all already possible.

It's already possible, until we find another bug in another CPU
model that also needs to be worked around. We can't represent
"please work around bugs in both Skylake and Westmere" in f/m/s.


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