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Subject[PATCH] x86/centaur: Mark TSC invariant
Centaur CPU has a constant frequency TSC and that TSC does not stop in C-States.
But because the flags are not set for that CPU, the TSC is treated as non constant
frequency and assumed to stop in C-States, which makes it an unreliable and unusable
clock source. Setting those flags tells the kernel that the TSC is usable, so it
will select it over HPET. The effect of this is that reading time stamps (from kernel
or userspace) will be faster and more efficient.

Signed-off-by: TimGuo <>
arch/x86/kernel/cpu/centaur.c | 4 ++++
drivers/acpi/processor_idle.c | 1 +
2 files changed, 5 insertions(+)

diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
index 68bc6d9..c578cd2 100644
--- a/arch/x86/kernel/cpu/centaur.c
+++ b/arch/x86/kernel/cpu/centaur.c
@@ -106,6 +106,10 @@ static void early_init_centaur(struct cpuinfo_x86 *c)
#ifdef CONFIG_X86_64
set_cpu_cap(c, X86_FEATURE_SYSENTER32);
+ if (c->x86_power & (1 << 8)) {
+ set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
+ set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
+ }

static void init_centaur(struct cpuinfo_x86 *c)
diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c
index d50a7b6..5f0071c 100644
--- a/drivers/acpi/processor_idle.c
+++ b/drivers/acpi/processor_idle.c
@@ -207,6 +207,7 @@ static void tsc_check_state(int state)
switch (boot_cpu_data.x86_vendor) {
case X86_VENDOR_AMD:
* AMD Fam10h TSC will tick in all
* C/P/S0/S1 states when this bit is set.

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