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Subject[RESEND PATCH 4/4] EDAC: add support for reduced-width Armada-XP SDRAM
Date
Some integrated Armada XP SoCs use a reduced pin count so the width of
the SDRAM interface is smaller than the traditional discrete SoCs. This
means that the definition of "full" and "half" width is further reduced.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---
drivers/edac/armada_xp_edac.c | 3 +++
1 file changed, 3 insertions(+)

diff --git a/drivers/edac/armada_xp_edac.c b/drivers/edac/armada_xp_edac.c
index 68e88b180928..d8edcaac87c0 100644
--- a/drivers/edac/armada_xp_edac.c
+++ b/drivers/edac/armada_xp_edac.c
@@ -350,6 +350,9 @@ static int armada_xp_mc_edac_probe(struct platform_device *pdev)
if (armada_xp_mc_edac_read_config(mci))
return -EINVAL;

+ if (of_property_read_bool(pdev->dev.of_node, "marvell,reduced-width"))
+ drvdata->width /= 2;
+
/* configure SBE threshold */
/* it seems that SBEs are not captured otherwise */
writel(1 << SDRAM_ERR_CTRL_ERR_THR_OFFSET,
--
2.13.0
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