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SubjectRe: [PATCH v6 4/4] perf vendor events arm64: Add ThunderX2 implementation defined pmu core events
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Hi Ganapat,

On 2017/8/24 20:03, Ganapatrao Kulkarni wrote:
> This is not a full event list, but a short list of useful events.
>
> Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
> ---
> tools/perf/pmu-events/arch/arm64/mapfile.csv | 15 ++++++
> .../arm64/thunderx2/implementation-defined.json | 62 ++++++++++++++++++++++
> 2 files changed, 77 insertions(+)
> create mode 100644 tools/perf/pmu-events/arch/arm64/mapfile.csv
> create mode 100644 tools/perf/pmu-events/arch/arm64/thunderx2/implementation-defined.json
>

I saw you also used thunderx2 in tools/perf/pmu-events/arch/arm64/, how about John's suggestion
that would use vendor sub-folder?
Of course, appreciate maintainer's comments.

Thanks,
Shaokun

> diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
> new file mode 100644
> index 0000000..7167086
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
> @@ -0,0 +1,15 @@
> +# Format:
> +# MIDR,Version,JSON/file/pathname,Type
> +#
> +# where
> +# MIDR Processor version
> +# Variant[23:20] and Revision [3:0] should be zero.
> +# Version could be used to track version of of JSON file
> +# but currently unused.
> +# JSON/file/pathname is the path to JSON file, relative
> +# to tools/perf/pmu-events/arch/arm64/.
> +# Type is core, uncore etc
> +#
> +#
> +#Family-model,Version,Filename,EventType
> +0x00000000420f5160,v1,thunderx2,core
> diff --git a/tools/perf/pmu-events/arch/arm64/thunderx2/implementation-defined.json b/tools/perf/pmu-events/arch/arm64/thunderx2/implementation-defined.json
> new file mode 100644
> index 0000000..2db45c4
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/arm64/thunderx2/implementation-defined.json
> @@ -0,0 +1,62 @@
> +[
> + {
> + "PublicDescription": "Attributable Level 1 data cache access, read",
> + "EventCode": "0x40",
> + "EventName": "l1d_cache_rd",
> + "BriefDescription": "L1D cache read",
> + },
> + {
> + "PublicDescription": "Attributable Level 1 data cache access, write ",
> + "EventCode": "0x41",
> + "EventName": "l1d_cache_wr",
> + "BriefDescription": "L1D cache write",
> + },
> + {
> + "PublicDescription": "Attributable Level 1 data cache refill, read",
> + "EventCode": "0x42",
> + "EventName": "l1d_cache_refill_rd",
> + "BriefDescription": "L1D cache refill read",
> + },
> + {
> + "PublicDescription": "Attributable Level 1 data cache refill, write",
> + "EventCode": "0x43",
> + "EventName": "l1d_cache_refill_wr",
> + "BriefDescription": "L1D refill write",
> + },
> + {
> + "PublicDescription": "Attributable Level 1 data TLB refill, read",
> + "EventCode": "0x4C",
> + "EventName": "l1d_tlb_refill_rd",
> + "BriefDescription": "L1D tlb refill read",
> + },
> + {
> + "PublicDescription": "Attributable Level 1 data TLB refill, write",
> + "EventCode": "0x4D",
> + "EventName": "l1d_tlb_refill_wr",
> + "BriefDescription": "L1D tlb refill write",
> + },
> + {
> + "PublicDescription": "Attributable Level 1 data or unified TLB access, read",
> + "EventCode": "0x4E",
> + "EventName": "l1d_tlb_rd",
> + "BriefDescription": "L1D tlb read",
> + },
> + {
> + "PublicDescription": "Attributable Level 1 data or unified TLB access, write",
> + "EventCode": "0x4F",
> + "EventName": "l1d_tlb_wr",
> + "BriefDescription": "L1D tlb write",
> + },
> + {
> + "PublicDescription": "Bus access read",
> + "EventCode": "0x60",
> + "EventName": "bus_access_rd",
> + "BriefDescription": "Bus access read",
> + },
> + {
> + "PublicDescription": "Bus access write",
> + "EventCode": "0x61",
> + "EventName": "bus_access_wr",
> + "BriefDescription": "Bus access write",
> + }
> +]
>

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