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Subject[PATCH 01/38] irqchip: mips-gic: SYNC after enabling GIC region
From: James Hogan <>

A SYNC is required between enabling the GIC region and actually trying
to use it, even if the first access is a read, otherwise its possible
depending on the timing (and in my case depending on the precise
alignment of certain kernel code) to hit CM bus errors on that first

Add the SYNC straight after setting the GIC base.

Changes later in this series increase our likelihood of hitting this
by reducing the amount of code that runs between enabling the GIC &
accessing it.]

Fixes: a7057270c280 ("irqchip: mips-gic: Add device-tree support")
Signed-off-by: James Hogan <>
Signed-off-by: Paul Burton <>
Cc: Thomas Gleixner <>
Cc: Jason Cooper <>
Cc: Marc Zyngier <>
Cc: Paul Burton <>
Cc: Ralf Baechle <>
Cc: <> # 3.19.x-

drivers/irqchip/irq-mips-gic.c | 3 +++
1 file changed, 3 insertions(+)

diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
index 9e984cefdca0..6841bd79c7c2 100644
--- a/drivers/irqchip/irq-mips-gic.c
+++ b/drivers/irqchip/irq-mips-gic.c
@@ -1022,6 +1022,9 @@ static int __init gic_of_init(struct device_node *node,

if (mips_cm_present())
write_gcr_gic_base(gic_base | CM_GCR_GIC_BASE_GICEN);
+ /* Ensure GIC region is enabled before trying to access it */
+ __sync();
+ }
gic_present = true;

__gic_init(gic_base, gic_len, cpu_vec, 0, node);
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