Messages in this thread |  | | Subject | Re: [PATCH v7 04/15] irqchip: RISC-V Local Interrupt Controller Driver | From | Randy Dunlap <> | Date | Tue, 1 Aug 2017 08:35:22 -0700 |
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On 07/31/2017 05:59 PM, Palmer Dabbelt wrote: > This patch adds a driver that manages the local interrupts on each > RISC-V hart, as specifiec by the RISC-V supervisor level ISA manual. > The local interrupt controller manages software interrupts, timer > interrupts, and hardware interrupts (which are routed via the > platform level interrupt controller). Per-hart local interrupt > controllers are found on all RISC-V systems. > > Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com> > --- > drivers/irqchip/Kconfig | 14 +++ > drivers/irqchip/Makefile | 1 + > drivers/irqchip/irq-riscv-intc.c | 213 +++++++++++++++++++++++++++++++++++++++ > 3 files changed, 228 insertions(+) > create mode 100644 drivers/irqchip/irq-riscv-intc.c
> diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c > new file mode 100644 > index 000000000000..96ae020cf1d5 > --- /dev/null > +++ b/drivers/irqchip/irq-riscv-intc.c > @@ -0,0 +1,213 @@ > +/* []
> + > +error_add_linear: > + pr_warning("%s: unable to add IRQ domain\n", > + data->name); > + return -(ENXIO); > +
Why the parentheses around ENXIO? Is it some macro calculation? Otherwise just use return -ENXIO; and drop the following blank line.
> +} > + > +IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init); >
-- ~Randy
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