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Subject[PATCH] doc: Update memory-barriers.txt for read-to-write dependencies
The memory-barriers.txt document contains an obsolete passage stating that
smp_read_barrier_depends() is required to force ordering for read-to-write
dependencies. We now know that this is not required, even for DEC Alpha.
This commit therefore updates this passage to state that read-to-write
dependencies are respected even without smp_read_barrier_depends().

Reported-by: Lance Roy <>
Signed-off-by: Paul E. McKenney <>
Cc: David Howells <>
Cc: Will Deacon <>
Cc: Peter Zijlstra <>
Cc: Jonathan Corbet <>
Cc: Alan Stern <>
Cc: Andrea Parri <>
Cc: Jade Alglave <>
Cc: Luc Maranget <>

diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt
index 9d5e0f853f08..a8a91b9d5a1b 100644
--- a/Documentation/memory-barriers.txt
+++ b/Documentation/memory-barriers.txt
@@ -594,7 +594,10 @@ between the address load and the data load:
This enforces the occurrence of one of the two implications, and prevents the
third possibility from arising.

-A data-dependency barrier must also order against dependent writes:
+A data-dependency barrier is not required to order dependent writes
+because the CPUs that the Linux kernel supports don't do writes until
+they are certain (1) that the write will actually happen, (2) of the
+location of the write, and (3) of the value to be written.

=============== ===============
@@ -603,19 +606,19 @@ A data-dependency barrier must also order against dependent writes:
<write barrier>
- <data dependency barrier>
*Q = 5;

-The data-dependency barrier must order the read into Q with the store
-into *Q. This prohibits this outcome:
+Therefore, no data-dependency barrier is required to order the read into
+Q with the store into *Q. In other words, this outcome is prohibited,
+even without a data-dependency barrier:

(Q == &B) && (B == 4)

Please note that this pattern should be rare. After all, the whole point
of dependency ordering is to -prevent- writes to the data structure, along
with the expensive cache misses associated with those writes. This pattern
-can be used to record rare error conditions and the like, and the ordering
-prevents such records from being lost.
+can be used to record rare error conditions and the like, and the CPUs'
+naturally occurring ordering prevents such records from being lost.

[!] Note that this extremely counterintuitive situation arises most easily on
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