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Subject[PATCH v2 2/7] staging: sm750fb: unifying macro usage and definitions
Date
This patch adds tabs into macro definitions so all rhs are on same column.
Removing MHz macro from ddk_chip.c file and reuse MHZ from sm750.h.

Signed-off-by: Matej Dujava <mdujava@kocurkovo.cz>
---
drivers/staging/sm750fb/ddk750_chip.c | 18 ++++----
drivers/staging/sm750fb/ddk750_display.h | 78 ++++++++++++++++----------------
drivers/staging/sm750fb/ddk750_hwi2c.c | 4 +-
drivers/staging/sm750fb/sm750.h | 6 +--
4 files changed, 52 insertions(+), 54 deletions(-)

diff --git a/drivers/staging/sm750fb/ddk750_chip.c b/drivers/staging/sm750fb/ddk750_chip.c
index 944dd25..64d0a53 100644
--- a/drivers/staging/sm750fb/ddk750_chip.c
+++ b/drivers/staging/sm750fb/ddk750_chip.c
@@ -5,8 +5,6 @@
#include "ddk750_chip.h"
#include "ddk750_power.h"

-#define MHz(x) ((x) * 1000000)
-
static logical_chip_type_t chip;

logical_chip_type_t sm750_get_chip_type(void)
@@ -36,7 +34,7 @@ static unsigned int get_mxclk_freq(void)
unsigned int M, N, OD, POD;

if (sm750_get_chip_type() == SM750LE)
- return MHz(130);
+ return MHZ(130);

pll_reg = peek32(MXCLK_PLL_CTRL);
M = (pll_reg & PLL_CTRL_M_MASK) >> PLL_CTRL_M_SHIFT;
@@ -98,8 +96,8 @@ static void set_memory_clock(unsigned int frequency)
* Set the frequency to the maximum frequency
* that the DDR Memory can take which is 336MHz.
*/
- if (frequency > MHz(336))
- frequency = MHz(336);
+ if (frequency > MHZ(336))
+ frequency = MHZ(336);

/* Calculate the divisor */
divisor = DIV_ROUND_CLOSEST(get_mxclk_freq(), frequency);
@@ -150,8 +148,8 @@ static void set_master_clock(unsigned int frequency)
* Set the frequency to the maximum frequency
* that the SM750 engine can run, which is about 190 MHz.
*/
- if (frequency > MHz(190))
- frequency = MHz(190);
+ if (frequency > MHZ(190))
+ frequency = MHZ(190);

/* Calculate the divisor */
divisor = DIV_ROUND_CLOSEST(get_mxclk_freq(), frequency);
@@ -237,13 +235,13 @@ int ddk750_init_hw(struct initchip_param *pInitParam)
}

/* Set the Main Chip Clock */
- set_chip_clock(MHz((unsigned int)pInitParam->chipClock));
+ set_chip_clock(MHZ((unsigned int)pInitParam->chipClock));

/* Set up memory clock. */
- set_memory_clock(MHz(pInitParam->memClock));
+ set_memory_clock(MHZ(pInitParam->memClock));

/* Set up master clock */
- set_master_clock(MHz(pInitParam->masterClock));
+ set_master_clock(MHZ(pInitParam->masterClock));

/*
* Reset the memory controller.
diff --git a/drivers/staging/sm750fb/ddk750_display.h b/drivers/staging/sm750fb/ddk750_display.h
index 609bf74..b34a2c6 100644
--- a/drivers/staging/sm750fb/ddk750_display.h
+++ b/drivers/staging/sm750fb/ddk750_display.h
@@ -6,83 +6,83 @@
* 80000[29:28]
*/

-#define PNL_2_OFFSET 0
-#define PNL_2_MASK (3 << PNL_2_OFFSET)
+#define PNL_2_OFFSET 0
+#define PNL_2_MASK (0x3 << PNL_2_OFFSET)
#define PNL_2_USAGE (PNL_2_MASK << 16)
-#define PNL_2_PRI ((0 << PNL_2_OFFSET) | PNL_2_USAGE)
-#define PNL_2_SEC ((2 << PNL_2_OFFSET) | PNL_2_USAGE)
+#define PNL_2_PRI ((0x0 << PNL_2_OFFSET) | PNL_2_USAGE)
+#define PNL_2_SEC ((0x2 << PNL_2_OFFSET) | PNL_2_USAGE)

/*
* primary timing & plane enable bit
* 1: 80000[8] & 80000[2] on
* 0: both off
*/
-#define PRI_TP_OFFSET 4
-#define PRI_TP_MASK BIT(PRI_TP_OFFSET)
-#define PRI_TP_USAGE (PRI_TP_MASK << 16)
-#define PRI_TP_ON ((0x1 << PRI_TP_OFFSET) | PRI_TP_USAGE)
-#define PRI_TP_OFF ((0x0 << PRI_TP_OFFSET) | PRI_TP_USAGE)
+#define PRI_TP_OFFSET 4
+#define PRI_TP_MASK BIT(PRI_TP_OFFSET)
+#define PRI_TP_USAGE (PRI_TP_MASK << 16)
+#define PRI_TP_ON ((0x1 << PRI_TP_OFFSET) | PRI_TP_USAGE)
+#define PRI_TP_OFF ((0x0 << PRI_TP_OFFSET) | PRI_TP_USAGE)

/*
* panel sequency status
* 80000[27:24]
*/
-#define PNL_SEQ_OFFSET 6
-#define PNL_SEQ_MASK BIT(PNL_SEQ_OFFSET)
-#define PNL_SEQ_USAGE (PNL_SEQ_MASK << 16)
-#define PNL_SEQ_ON (BIT(PNL_SEQ_OFFSET) | PNL_SEQ_USAGE)
-#define PNL_SEQ_OFF ((0 << PNL_SEQ_OFFSET) | PNL_SEQ_USAGE)
+#define PNL_SEQ_OFFSET 6
+#define PNL_SEQ_MASK BIT(PNL_SEQ_OFFSET)
+#define PNL_SEQ_USAGE (PNL_SEQ_MASK << 16)
+#define PNL_SEQ_ON ((0x1 << PNL_SEQ_OFFSET) | PNL_SEQ_USAGE)
+#define PNL_SEQ_OFF ((0x0 << PNL_SEQ_OFFSET) | PNL_SEQ_USAGE)

/*
* dual digital output
* 80000[19]
*/
-#define DUAL_TFT_OFFSET 8
-#define DUAL_TFT_MASK BIT(DUAL_TFT_OFFSET)
-#define DUAL_TFT_USAGE (DUAL_TFT_MASK << 16)
-#define DUAL_TFT_ON (BIT(DUAL_TFT_OFFSET) | DUAL_TFT_USAGE)
-#define DUAL_TFT_OFF ((0 << DUAL_TFT_OFFSET) | DUAL_TFT_USAGE)
+#define DUAL_TFT_OFFSET 8
+#define DUAL_TFT_MASK BIT(DUAL_TFT_OFFSET)
+#define DUAL_TFT_USAGE (DUAL_TFT_MASK << 16)
+#define DUAL_TFT_ON ((0x1 << DUAL_TFT_OFFSET) | DUAL_TFT_USAGE)
+#define DUAL_TFT_OFF ((0x0 << DUAL_TFT_OFFSET) | DUAL_TFT_USAGE)

/*
* secondary timing & plane enable bit
* 1:80200[8] & 80200[2] on
* 0: both off
*/
-#define SEC_TP_OFFSET 5
-#define SEC_TP_MASK BIT(SEC_TP_OFFSET)
-#define SEC_TP_USAGE (SEC_TP_MASK << 16)
-#define SEC_TP_ON ((0x1 << SEC_TP_OFFSET) | SEC_TP_USAGE)
-#define SEC_TP_OFF ((0x0 << SEC_TP_OFFSET) | SEC_TP_USAGE)
+#define SEC_TP_OFFSET 5
+#define SEC_TP_MASK BIT(SEC_TP_OFFSET)
+#define SEC_TP_USAGE (SEC_TP_MASK << 16)
+#define SEC_TP_ON ((0x1 << SEC_TP_OFFSET) | SEC_TP_USAGE)
+#define SEC_TP_OFF ((0x0 << SEC_TP_OFFSET) | SEC_TP_USAGE)

/*
* crt path select
* 80200[19:18]
*/
-#define CRT_2_OFFSET 2
-#define CRT_2_MASK (3 << CRT_2_OFFSET)
-#define CRT_2_USAGE (CRT_2_MASK << 16)
-#define CRT_2_PRI ((0x0 << CRT_2_OFFSET) | CRT_2_USAGE)
-#define CRT_2_SEC ((0x2 << CRT_2_OFFSET) | CRT_2_USAGE)
+#define CRT_2_OFFSET 2
+#define CRT_2_MASK (0x3 << CRT_2_OFFSET)
+#define CRT_2_USAGE (CRT_2_MASK << 16)
+#define CRT_2_PRI ((0x0 << CRT_2_OFFSET) | CRT_2_USAGE)
+#define CRT_2_SEC ((0x2 << CRT_2_OFFSET) | CRT_2_USAGE)

/*
* DAC affect both DVI and DSUB
* 4[20]
*/
-#define DAC_OFFSET 7
-#define DAC_MASK BIT(DAC_OFFSET)
-#define DAC_USAGE (DAC_MASK << 16)
-#define DAC_ON ((0x0 << DAC_OFFSET) | DAC_USAGE)
-#define DAC_OFF ((0x1 << DAC_OFFSET) | DAC_USAGE)
+#define DAC_OFFSET 7
+#define DAC_MASK BIT(DAC_OFFSET)
+#define DAC_USAGE (DAC_MASK << 16)
+#define DAC_ON ((0x0 << DAC_OFFSET) | DAC_USAGE)
+#define DAC_OFF ((0x1 << DAC_OFFSET) | DAC_USAGE)

/*
* DPMS only affect D-SUB head
* 0[31:30]
*/
-#define DPMS_OFFSET 9
-#define DPMS_MASK (3 << DPMS_OFFSET)
-#define DPMS_USAGE (DPMS_MASK << 16)
-#define DPMS_OFF ((3 << DPMS_OFFSET) | DPMS_USAGE)
-#define DPMS_ON ((0 << DPMS_OFFSET) | DPMS_USAGE)
+#define DPMS_OFFSET 9
+#define DPMS_MASK (0x3 << DPMS_OFFSET)
+#define DPMS_USAGE (DPMS_MASK << 16)
+#define DPMS_ON ((0x0 << DPMS_OFFSET) | DPMS_USAGE)
+#define DPMS_OFF ((0x3 << DPMS_OFFSET) | DPMS_USAGE)

/*
* LCD1 means panel path TFT1 & panel path DVI (so enable DAC)
diff --git a/drivers/staging/sm750fb/ddk750_hwi2c.c b/drivers/staging/sm750fb/ddk750_hwi2c.c
index ec556a9..ccf49ef 100644
--- a/drivers/staging/sm750fb/ddk750_hwi2c.c
+++ b/drivers/staging/sm750fb/ddk750_hwi2c.c
@@ -5,8 +5,8 @@
#include "ddk750_hwi2c.h"
#include "ddk750_power.h"

-#define MAX_HWI2C_FIFO 16
-#define HWI2C_WAIT_TIMEOUT 0xF0000
+#define MAX_HWI2C_FIFO 16
+#define HWI2C_WAIT_TIMEOUT 0xF0000

int sm750_hw_i2c_init(unsigned char bus_speed_mode)
{
diff --git a/drivers/staging/sm750fb/sm750.h b/drivers/staging/sm750fb/sm750.h
index 5b186da..1e21fa1 100644
--- a/drivers/staging/sm750fb/sm750.h
+++ b/drivers/staging/sm750fb/sm750.h
@@ -1,14 +1,14 @@
#ifndef LYNXDRV_H_
#define LYNXDRV_H_

-#define FB_ACCEL_SMI 0xab
+#define FB_ACCEL_SMI 0xab

-#define MHZ(x) ((x) * 1000000)
+#define MHZ(x) ((x) * 1000000)

#define DEFAULT_SM750_CHIP_CLOCK 290
#define DEFAULT_SM750LE_CHIP_CLOCK 333
#ifndef SM750LE_REVISION_ID
-#define SM750LE_REVISION_ID ((unsigned char)0xfe)
+#define SM750LE_REVISION_ID ((unsigned char)0xfe)
#endif

enum sm750_pnltype {
--
1.8.3.1
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