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Subject[PATCH] irqchip/riscv-plic: fix address alignment of the plic enable bits
Date
When the interrupt sourece id > 31, the register address is not 4 byte
alignment. Arithmetic on void pointer has no size extension, it just
add the result of 'hwirq/32' directly.

Signed-off-by: Zong Li <zongbox@gmail.com>
---
drivers/irqchip/irq-riscv-plic.c | 15 +++++++++------
1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/drivers/irqchip/irq-riscv-plic.c b/drivers/irqchip/irq-riscv-plic.c
index b5182b4..0a43763 100644
--- a/drivers/irqchip/irq-riscv-plic.c
+++ b/drivers/irqchip/irq-riscv-plic.c
@@ -92,6 +92,8 @@
*/
#define ENABLE_BASE 0x2000
#define ENABLE_PER_HART 0x80
+#define ENABLE_SOURCES 32
+#define ENABLE_SOURCES_OFFSET 4

/*
* Each hart context has a set of control registers associated with it. Right
@@ -128,9 +130,10 @@ struct plic_data {

/* Addressing helper functions. */
static inline
-void __iomem *plic_enable_vector(struct plic_data *data, int contextid)
+void __iomem *plic_enable_vector(struct plic_data *data, int contextid, int hwirq)
{
- return data->reg + ENABLE_BASE + contextid * ENABLE_PER_HART;
+ return data->reg + ENABLE_BASE + contextid * ENABLE_PER_HART +
+ (hwirq / ENABLE_SOURCES) * ENABLE_SOURCES_OFFSET;
}

static inline
@@ -172,8 +175,8 @@ void plic_complete(struct plic_data *data, int contextid, u32 claim)
/* Explicit interrupt masking. */
static void plic_disable(struct plic_data *data, int contextid, int hwirq)
{
- void __iomem *reg = plic_enable_vector(data, contextid) + (hwirq / 32);
- u32 mask = ~(1 << (hwirq % 32));
+ void __iomem *reg = plic_enable_vector(data, contextid, hwirq);
+ u32 mask = ~(1 << (hwirq % ENABLE_SOURCES));

spin_lock(&data->lock);
writel(readl(reg) & mask, reg);
@@ -182,8 +185,8 @@ static void plic_disable(struct plic_data *data, int contextid, int hwirq)

static void plic_enable(struct plic_data *data, int contextid, int hwirq)
{
- void __iomem *reg = plic_enable_vector(data, contextid) + (hwirq / 32);
- u32 bit = 1 << (hwirq % 32);
+ void __iomem *reg = plic_enable_vector(data, contextid, hwirq);
+ u32 bit = 1 << (hwirq % ENABLE_SOURCES);

spin_lock(&data->lock);
writel(readl(reg) | bit, reg);
--
2.7.4
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