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SubjectRe: [PATCH] drm/bridge: analogix_dp: Use relaxed MMIO accessors
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On 18.12.2017 12:39, Marc Zyngier wrote:
> The analogix DP bridge is entierely driven via MMIO accesses, and
> does not do any DMA that requires coherency with the CPU. Yet, the
> driver uses the non-relaxed accessors, forcing strong barriers to
> be emitted on architectures with a relaxed memory ordering.
>
> This is of course completely unnecessary, and only serves as a way
> to pointlessly reduce the performance of unsuspecting platforms.
>
> Switch the driver to the _relaxed accessors, making my kevin platform
> a slightly better machine.

Do you have any stats to justify this change?
The common practice is/was to use writel/readl accessors to access MMIO,
even if it is suboptimal in many cases. Has something changed in these
practices?
To be clear, I am not against this change. I am just curious.

Regards
Andrzej


>
> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
> ---
> drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 488 +++++++++++-----------
> 1 file changed, 244 insertions(+), 244 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> index 303083ad28e3..248d6ba913dc 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> @@ -31,13 +31,13 @@ void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable)
> u32 reg;
>
> if (enable) {
> - reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
> + reg = readl_relaxed(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
> reg |= HDCP_VIDEO_MUTE;
> - writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
> + writel_relaxed(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
> } else {
> - reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
> + reg = readl_relaxed(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
> reg &= ~HDCP_VIDEO_MUTE;
> - writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
> + writel_relaxed(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
> }
> }
...

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