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SubjectRe: [PATCH v3 09/33] nds32: Cache and TLB routines
On Fri, Dec 08, 2017 at 05:11:52PM +0800, Greentime Hu wrote:
> From: Greentime Hu <greentime@andestech.com>
[...]
> diff --git a/arch/nds32/mm/cacheflush.c b/arch/nds32/mm/cacheflush.c
[...]
> +#ifndef CONFIG_CPU_CACHE_ALIASING
> +void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
> + pte_t * pte)
[...]
> + if (vma->vm_mm == current->active_mm) {
> +
> + __nds32__mtsr_dsb(addr, NDS32_SR_TLB_VPN);
> + __nds32__tlbop_rwr(*pte);
> + __nds32__isb();
If there is an interruption between "mtsr_dsb" and "tlbop_rwr" and a
update_mmu_cache() is invoked again, then an error page mapping is
set up in your tlb-buffer when tlbop_rwr is excuted from interrupt.
Because it's another addr in NDS32_SR_TLB_VPN.

It seems that tlb-hardrefill can help build tlb-buffer mapping, why you
update it in this software way?

Guo Ren

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