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SubjectRe: [PATCH 01/13] perf/core: Add perf_arch_regs and mask to perf_regs structure
On Tue, Sep 06, 2016 at 09:55:43AM +0530, Madhavan Srinivasan wrote:
> On Thursday 01 September 2016 12:56 PM, Peter Zijlstra wrote:
> >On Mon, Aug 29, 2016 at 02:30:46AM +0530, Madhavan Srinivasan wrote:
> >>It's a perennial request from hardware folks to be able to
> >>see the raw values of the pmu registers. Partly it's so that
> >>they can verify perf is doing what they want, and some
> >>of it is that they're interested in some of the more obscure
> >>info that isn't plumbed out through other perf interfaces.
> >How much and what is that? Can't we try and get interfaces sorted?
> We have bunch of registers which exports information regarding the
> sampled instruction like SIER/SIAR/SDAR/MMCRA. Lot of bits in these
> registers are not yet architected and incase of SIER register, some of
> the bits are not plumbed out and we are working on getting some these
> exposed via perf.

What kind of information is this? I'm not familiar with the Power PMU
all that much, so you'll have to spell it out, not just mention the
registers its stuffed in.

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