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    Subject[PATCH 4.4 065/118] pinctrl: sunxi: fix uart1 CTS/RTS pins at PG on A23/A33
    Date
    4.4-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Icenowy Zheng <icenowy@aosc.xyz>

    commit 486095fae3a8a6b1ae07c51844699d9bd5cfbebc upstream.

    PG8, PG9 is said to be the CTS/RTS pins for UART1 according to the A23/33
    datasheets. However, the function is wrongly named "uart2" in the pinctrl
    driver. This patch fixes this by modifying them to be named "uart1".

    Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
    Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
    Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

    ---
    drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c | 4 ++--
    drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c | 4 ++--
    2 files changed, 4 insertions(+), 4 deletions(-)

    --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c
    +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c
    @@ -485,12 +485,12 @@ static const struct sunxi_desc_pin sun8i
    SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
    SUNXI_FUNCTION(0x0, "gpio_in"),
    SUNXI_FUNCTION(0x1, "gpio_out"),
    - SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
    + SUNXI_FUNCTION(0x2, "uart1"), /* RTS */
    SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 8)), /* PG_EINT8 */
    SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
    SUNXI_FUNCTION(0x0, "gpio_in"),
    SUNXI_FUNCTION(0x1, "gpio_out"),
    - SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
    + SUNXI_FUNCTION(0x2, "uart1"), /* CTS */
    SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 9)), /* PG_EINT9 */
    SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
    SUNXI_FUNCTION(0x0, "gpio_in"),
    --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
    +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
    @@ -407,12 +407,12 @@ static const struct sunxi_desc_pin sun8i
    SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
    SUNXI_FUNCTION(0x0, "gpio_in"),
    SUNXI_FUNCTION(0x1, "gpio_out"),
    - SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
    + SUNXI_FUNCTION(0x2, "uart1"), /* RTS */
    SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 8)), /* PG_EINT8 */
    SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
    SUNXI_FUNCTION(0x0, "gpio_in"),
    SUNXI_FUNCTION(0x1, "gpio_out"),
    - SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
    + SUNXI_FUNCTION(0x2, "uart1"), /* CTS */
    SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 9)), /* PG_EINT9 */
    SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
    SUNXI_FUNCTION(0x0, "gpio_in"),

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