Messages in this thread |  | | Date | Sun, 30 Oct 2016 19:14:17 -0600 (MDT) | From | Thomas Gleixner <> | Subject | Re: [PATCH v7 1/4] x86/msr: Add MSR(140H) and PHIR3MWAIT bit to msr-info.h |
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On Fri, 28 Oct 2016, Grzegorz Andrejczuk wrote:
> Subject: x86/msr: Add MSR(140H) and PHIR3MWAIT bit to msr-info.h
What kind of information is this: MSR(140h)? None at all. That MSR has a name. So why not using it?
x86/msr: Add MSR_MISC_FEATURE_ENABLES and PHIR3MWAIT bit
Hmm? You might have noticed that I removed the 'to msr-info.h' part. I did this because it's useless information. We can see that from the patch.
> Intel Xeon Phi x200 (codenamed Knights Landing) has MSR > MISC_FEATURE_ENABLES 0x140.
And that tells us what?
> Setting 2nd bit of this register makes MONITOR and MWAIT instructions > do not cause invalid-opcode exception when called from ring different > than 0.
Can you please be a bit more careful with your changelogs? I give you an example for a proper one:
Intel Xeon Phi x200 (codenamed Knights Landing) allows to enable MONITOR and MWAIT instructions outside of ring 0.
The feature is controlled by MSR MISC_FEATURE_ENABLES (0x144). Setting bit 0 of this register enables it, so MONITOR and MWAIT instructions do not cause invalid-opcode exceptions when invoked outside of ring 0.
The feature MSR is not yet documented in the SDM. Here is the relevant documentation:
Can you spot the difference?
Hint: Copy and paste are dangerous
> --- a/arch/x86/include/asm/msr-index.h > +++ b/arch/x86/include/asm/msr-index.h > @@ -540,6 +540,11 @@ > #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39 > #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT) > > +/* Intel Xeon Phi x200 ring 3 MONITOR/MWAIT */ > +#define MSR_MISC_FEATURE_ENABLES 0x00000140 > +#define MSR_MISC_FEATURE_ENABLES_PHIR3MWAIT_BIT 1 > +#define MSR_MISC_FEATURE_ENABLES_PHIR3MWAIT (1ULL << MSR_MISC_FEATURE_ENABLES_PHIR3MWAIT_BIT) > +
See comment on patch 4/4 why this bit mask is not required.
Thanks,
tglx
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