Messages in this thread Patch in this message |  | | From | David Carrillo-Cisneros <> | Subject | [PATCH v3 02/46] perf/x86/intel: rename CQM cpufeatures to CMT | Date | Sat, 29 Oct 2016 17:37:59 -0700 |
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CMT name has superseded CQM in Intel's documentation.
Rename cpufeatures. Next patches in this series will use the CMT name.
Signed-off-by: David Carrillo-Cisneros <davidcc@google.com> --- arch/x86/include/asm/cpufeatures.h | 14 +++++++------- arch/x86/kernel/cpu/common.c | 10 +++++----- 2 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 90b8c0b..cd3b215 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -222,7 +222,7 @@ #define X86_FEATURE_ERMS ( 9*32+ 9) /* Enhanced REP MOVSB/STOSB */ #define X86_FEATURE_INVPCID ( 9*32+10) /* Invalidate Processor Context ID */ #define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional Memory */ -#define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */ +#define X86_FEATURE_CMT ( 9*32+12) /* Cache Monitoring Technology */ #define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection Extension */ #define X86_FEATURE_RDT_A ( 9*32+15) /* Resource Director Technology Allocation */ #define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */ @@ -245,13 +245,13 @@ #define X86_FEATURE_XGETBV1 (10*32+ 2) /* XGETBV with ECX = 1 */ #define X86_FEATURE_XSAVES (10*32+ 3) /* XSAVES/XRSTORS */ -/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:0 (edx), word 11 */ -#define X86_FEATURE_CQM_LLC (11*32+ 1) /* LLC QoS if 1 */ +/* Intel-defined CPU CMT Sub-leaf, CPUID level 0x0000000F:0 (edx), word 11 */ +#define X86_FEATURE_CMT_LLC (11*32+ 1) /* LLC CMT if 1 */ -/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (edx), word 12 */ -#define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring if 1 */ -#define X86_FEATURE_CQM_MBM_TOTAL (12*32+ 1) /* LLC Total MBM monitoring */ -#define X86_FEATURE_CQM_MBM_LOCAL (12*32+ 2) /* LLC Local MBM monitoring */ +/* Intel-defined CPU CMT Sub-leaf, CPUID level 0x0000000F:1 (edx), word 12 */ +#define X86_FEATURE_CMT_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring if 1 */ +#define X86_FEATURE_CMT_MBM_TOTAL (12*32+ 1) /* LLC Total MBM monitoring */ +#define X86_FEATURE_CMT_MBM_LOCAL (12*32+ 2) /* LLC Local MBM monitoring */ /* AMD-defined CPU features, CPUID level 0x80000008 (ebx), word 13 */ #define X86_FEATURE_CLZERO (13*32+0) /* CLZERO instruction */ diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 9bd910a..911ee16 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -691,7 +691,7 @@ void get_cpu_cap(struct cpuinfo_x86 *c) cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx); c->x86_capability[CPUID_F_0_EDX] = edx; - if (cpu_has(c, X86_FEATURE_CQM_LLC)) { + if (cpu_has(c, X86_FEATURE_CMT_LLC)) { /* will be overridden if occupancy monitoring exists */ c->x86_cache_max_rmid = ebx; @@ -699,9 +699,9 @@ void get_cpu_cap(struct cpuinfo_x86 *c) cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx); c->x86_capability[CPUID_F_1_EDX] = edx; - if ((cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) || - ((cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL)) || - (cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)))) { + if ((cpu_has(c, X86_FEATURE_CMT_OCCUP_LLC)) || + ((cpu_has(c, X86_FEATURE_CMT_MBM_TOTAL)) || + (cpu_has(c, X86_FEATURE_CMT_MBM_LOCAL)))) { c->x86_cache_max_rmid = ecx; c->x86_cache_occ_scale = ebx; } @@ -969,7 +969,7 @@ static void x86_init_cache_qos(struct cpuinfo_x86 *c) /* * The heavy lifting of max_rmid and cache_occ_scale are handled * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu - * in case CQM bits really aren't there in this CPU. + * in case CMT bits really aren't there in this CPU. */ if (c != &boot_cpu_data) { boot_cpu_data.x86_cache_max_rmid = -- 2.8.0.rc3.226.g39d4020
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