[lkml]   [2016]   [Oct]   [14]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
Messages in this thread
SubjectRe: [PATCH] irqchip/gic: Enable gic_set_affinity set more than one cpu
On 14/10/16 03:08, Cheng Chao wrote:
> Marc,
> Thanks for your comments.
> Cheng
> on 10/13/2016 11:31 PM, Marc Zyngier wrote:
>> On Thu, 13 Oct 2016 18:57:14 +0800
>> Cheng Chao <> wrote:
>>> GIC can distribute an interrupt to more than one cpu,
>>> but now, gic_set_affinity sets only one cpu to handle interrupt.
>> What makes you think this is a good idea? What purpose does it serves?
>> I can only see drawbacks to this: You're waking up more than one CPU,
>> wasting power, adding jitter and clobbering the cache.
>> I assume you see a benefit to that approach, so can you please spell it
>> out?
> Ok, You are right, but the performance is another point that we should consider.
> We use E1 device to transmit/receive video stream. we find that E1's interrupt is
> only on the one cpu that cause this cpu usage is almost 100%,
> but other cpus is much lower load, so the performance is not good.
> the cpu is 4-core.

It looks to me like you're barking up the wrong tree. We have
NAPI-enabled network drivers for this exact reason, and adding more
interrupts to an already overloaded system doesn't strike me as going in
the right direction. May I suggest that you look at integrating NAPI
into your E1 driver?

> thus we can make a trade-off between the performance with the power etc.

No, that's pretty horrible, and I'm not even going to entertain the
idea. I suggest you start investigating how to mitigate your interrupt
rate instead of just taking more of them.


Jazz is not dead. It just smells funny...

 \ /
  Last update: 2016-10-14 19:34    [W:0.122 / U:0.760 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site