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SubjectRe: [PATCH] MIPS: OCTEON: Use correct CSR to soft reset
On 03/05/2015 07:06 AM, Aleksey Makarov wrote:
> From: Chandrakala Chavva <cchavva@caviumnetworks.com>
>
> This fixes reboot for Octeon III boards
>
> Signed-off-by: Chandrakala Chavva <cchavva@caviumnetworks.com>
> Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>

Let's make a change to this patch...

> ---
> arch/mips/cavium-octeon/setup.c | 5 ++++-
> arch/mips/include/asm/octeon/cvmx.h | 6 +++++-
> 2 files changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
> index 01130e9..73348af 100644
> --- a/arch/mips/cavium-octeon/setup.c
> +++ b/arch/mips/cavium-octeon/setup.c
> @@ -416,7 +416,10 @@ static void octeon_restart(char *command)
>
> mb();
> while (1)
> - cvmx_write_csr(CVMX_CIU_SOFT_RST, 1);
> + if (OCTEON_IS_OCTEON3())
> + cvmx_write_csr(CVMX_RST_SOFT_RST, 1);
> + else
> + cvmx_write_csr(CVMX_CIU_SOFT_RST, 1);
> }
>
>
> diff --git a/arch/mips/include/asm/octeon/cvmx.h b/arch/mips/include/asm/octeon/cvmx.h
> index 33db1c8..fb575d7 100644
> --- a/arch/mips/include/asm/octeon/cvmx.h
> +++ b/arch/mips/include/asm/octeon/cvmx.h
> @@ -66,6 +66,7 @@ enum cvmx_mips_space {
> #include <asm/octeon/cvmx-led-defs.h>
> #include <asm/octeon/cvmx-mio-defs.h>
> #include <asm/octeon/cvmx-pow-defs.h>
> +#include <asm/octeon/cvmx-rst-defs.h>
>
> #include <asm/octeon/cvmx-bootinfo.h>
> #include <asm/octeon/cvmx-bootmem.h>
> @@ -441,7 +442,10 @@ static inline void cvmx_reset_octeon(void)
> union cvmx_ciu_soft_rst ciu_soft_rst;
> ciu_soft_rst.u64 = 0;
> ciu_soft_rst.s.soft_rst = 1;
> - cvmx_write_csr(CVMX_CIU_SOFT_RST, ciu_soft_rst.u64);
> + if (OCTEON_IS_OCTEON3())
> + cvmx_write_csr(CVMX_RST_SOFT_RST, ciu_soft_rst.u64);
> + else
> + cvmx_write_csr(CVMX_CIU_SOFT_RST, ciu_soft_rst.u64);
> }


cvmx_reset_octeon() is unused in the kernel. So instead of patching it
up, remove it altogether, thus removing a little bit of ugliness from
the world.

David Daney




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