| From | Jiri Slaby <> | Subject | [PATCH 3.12 026/122] mmc: sdhci-pci: Fix Braswell eMMC timeout clock frequency | Date | Tue, 17 Feb 2015 12:33:33 +0100 |
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From: Adrian Hunter <adrian.hunter@intel.com>
3.12-stable review patch. If anyone has any objections, please let me know.
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commit a06586b62db5c63752e2e68daffec4baa275d594 upstream.
Braswell eMMC host controller specifies an incorrect timeout clock frequncy in the capabilities registers. The correct value is 1 MHz.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Jiri Slaby <jslaby@suse.cz> --- drivers/mmc/host/sdhci-pci.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/drivers/mmc/host/sdhci-pci.c b/drivers/mmc/host/sdhci-pci.c index a130a11d89de..730527af71d7 100644 --- a/drivers/mmc/host/sdhci-pci.c +++ b/drivers/mmc/host/sdhci-pci.c @@ -270,6 +270,8 @@ static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) MMC_CAP_HW_RESET; slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ; slot->hw_reset = sdhci_pci_int_hw_reset; + if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) + slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ return 0; } -- 2.2.2
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