Messages in this thread |  | | Date | Mon, 16 Feb 2015 17:49:20 +0100 | From | Maxime Ripard <> | Subject | Re: [PATCH v3 1/2] mtd: nand: pxa3xx: Fix PIO FIFO draining |
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On Mon, Feb 16, 2015 at 10:35:50AM -0300, Ezequiel Garcia wrote: > On 02/16/2015 09:51 AM, Maxime Ripard wrote: > > The NDDB register holds the data that are needed by the read and write > > commands. > > > > However, during a read PIO access, the datasheet specifies that after each 32 > > bits read in that register, when BCH is enabled, we have to make sure that the > > RDDREQ bit is set in the NDSR register. > > > > Typo s/32 bits/32 bytes
Good catch, thanks! Maxime
-- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com [unhandled content-type:application/pgp-signature] |  |