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Subject[question] on which cpu an interrupt controller will raise an irq ?

Hi all,

I am not very familiar with the interrupt subsystem, so sorry if this
sounds a stupid question.

IIUC, when a interrupt happens on a SMP system and if there is no
affinity set for it, it is delivered following a scheme decided by the
interrupt controller.

For example, for the APIC, there is a round robin behaviour, so an
interrupt will be raised on cpu0, then cpu1, and so on ...

Is there a way to know on which cpu a controller will raise the interrupt ?

Thanks in advance

-- Daniel

<> │ Open source software for ARM SoCs

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